Specifications

112 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 6: Simulation Model Generator
R
Timing Models
To create a timing simulation model, SimGen requires an MHS file as input and associated
implemented netlist file. From this netlist file SimGen will create an hdl file that models the
design and an SDF file with appropriate timing information for it. Optionally, SimGen can
generate a compile script for a specified vendor simulator. Also not required but if
specified, SimGen can generate hdl files with data to initialize brams associated with any
processor that may exist in the design. This data is obtained from an existing executable elf
file.
SimGen Syntax
At the prompt, execute SimGen with the MHS file and appropriate options as inputs.
For example,
simgen system_name.mhs [options]
Requirements
Set up your system to use the Xilinx ISE tools. Verify that your system is properly
configured. Consult the release notes and installation notes that came with your software
package for more information.
Options
The following options are supported in the current version:
Help
-h, -help
The -h option displays the usage menu and quits.
Version
-v
The -v option displays the version and quits.
Figure 6-4: Timing simulation model generation
UG111_04_111903
mhs
elf
SimGen
Script
HDL
ncd