Specifications

110 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 6: Simulation Model Generator
R
To print the COMPEDKLIB online help to your monitor screen, type the following at the
command line:
compedklib -h
COMPEDKLIB Command Line Examples
Use Case I: Compiling HDL sources in the built-in repositories in the EDK
The most common use case is as follows:
compedklib -o <compedklib-output-dir-name>
-X <compxlib-output-dir-name>
In this case the pcores available in the EDK install are compiled and the stored in
<compedklib-output-dir-name>. The value to the ’-X’ option indicates the directory
containing the models outputted by COMPXLIB, such as the unisim, simprim and
XilinxCoreLib compiled libraries.
Use Case II: Compiling HDL sources in your own repository
If you had your own repository of EDK style pcores, you may to compile them into
<compedklib-output-dir-name> as follows:
compedklib -o <compedklib-output-dir-name>
-X <compxlib-output-dir-name>
-E <compedklib-output-dir-name>
-lp <Your-Repository-Dir>
In this form, the ’-E’ value accounts for the possibility that some of the pcores in your
repository may need to access the compiled models generated by Use Case I. This is very
likely because the pcores in your repository are likely to refer to HDL sources in the EDK
built-in repositories.
Other details
You can supply multiple ’-X’ and ’-E’ arguments. The order is important. If you have the
same pcore in two places, the first one is used.
Some pcores are secure in that their source code is not available. In such cases, the
repository contains the compiled models. These are copied out into <compedklib-
output-dir-name>.
If your pcores are in your XPS project, you do not need to bother about Use Case 2.
XPS/SIMGEN will create the scripts to compile them.
If you have the MODELSIM environment variable set, the modelsim.ini file that it points to
gets modified when this tool is compiling the HDL sources for MTI SE/PE.
Presently only VHDL is supported.
The execution log is available in compedklib.log.
Simulation Models
This section describes how to generate each of the three FPGA simulation stages. For each
stage, a different simulation model can be created by SimGen.