Specifications

108 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 6: Simulation Model Generator
R
Simulation Basics
This section introduces the basic facts and terminology of HDL simulation in EDK. There
are three stages in the FPGA design process in which you conduct verification through
simulation. Figure 6-1 shows these stages.
Behavioral simulation is used to verify the syntax and functionality without timing
information. The majority of the design development is done through behavioral
simulation until the required functionality is obtained. Errors identified early in the design
cycle are inexpensive to fix compared to functional errors identified during silicon debug.
Structural Simulation
After the behavioral simulation is error free, the HDL design is synthesized to gates. The
post-synthesized structural simulation is a functional simulation with unit delay timing.
The simulation can be used to identify initialization issues and to analyze don’t care
conditions. The post synthesis simulation generally uses the same testbench as functional
simulation.
Timing Simulation
Structural timing simulation is a back-annotated timing simulation. Timing simulation is
important in verifying the operation of your circuit after the worst case place and route
delays are calculated for your design. The back annotation process produces a netlist of
library components annotated in an SDF file with the appropriate block and net delays
from the place and route process. The simulation will identify any race conditions and
setup-and-hold violations based on the operating conditions for the specified functionality.
Simulation Libraries
The following libraries are available for the Xilinx simulation flow.The HDL code must
refer to the appropriate compiled library. The HDL simulator must map the logical library
to the physical location of the compiled library.
Xilinx Libraries
The following libraries are provided by Xilinx for simulation. These libraries can be
compiled using COMPXLIB. Please refer to Chapter 6, “Verifying Your Design” in the
Synthesis and Verification Design Guide in your ISE 6.1 distribution to learn more about
compiling and using Xilinx simulation libraries.
Figure 6-1: FPGA design simulation stages
Behavioral
Simulation
Functional Simulation
Design
Entry
Design
Synthesis
Design
Netlist
Design
Implementation
Implemented
Design Netlist
Timing
Simulation
Structural
Simulation
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