Specifications

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Chapter 6
Simulation Model Generator
This chapter introduces the basics of HDL simulation and describes the Simulation Model
Generator tool and COMPEDKLIB utility usage. It contains the following sections.
x “Overview”
x “Simulation Basics”
x “Compiling EDK Simulation Libraries”
x “Simulation Models”
x “SimGen Syntax”
x “Output Files”
x “Memory Initialization”
x “Simulating Your Design”
x “Current Limitations”
Overview
The Simulation Model Generator (SimGen) creates and configures various VHDL and
Verilog simulation models for a specified hardware. It takes a Microprocessor Hardware
Specification (MHS) file as input that describes the hardware.
SimGen is also capable of creating scripts for a specified vendor simulation tool. The
scripts compile the generated simulation models.
The hardware component is defined by the Microprocessor Hardware Specification (MHS)
file. Please refer to Chapter 15, “Microprocessor Hardware Specification (MHS)” for more
information.