Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 105
UG111 (v1.4) January 30, 2004 1-800-255-7778
Synthesis Netlist Cache
R
Synthesis Netlist Cache
An IP rebuild occurs with one of the following fundamental changes:
x Instance name change
x Parameter value change
x Core version change
x Core is specified with the MPD “CORE_STATE=DEVELOPMENT” option
At least one of the above conditions is occurring to trigger an IP rebuild.
Current Limitations
The current limitations of the PlatGen flow are:
x Vector slicing is not allowed.
C_OPB_NUM_SLAVES Number of OPB slaves
C_PLB_AWIDTH PLB Address width
C_PLB_DWIDTH PLB Data width
C_PLB_MID_WIDTH PLB master ID width
C_PLB_NUM_MASTERS Number of PLB masters
C_PLB_NUM_SLAVES Number of PLB slaves
Table 5-2: Automatically Expanded Reserved Parameters
Parameter Description