Specifications

CHAPTER 5: PLACE & ROUTE
INTRODUCTION
90 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Introduction
The Quartus
®
II Fitter, which is also known as the PowerFit
™
Fitter,
performs place and route, which is also referred to as “fitting” in the
Quartus II software. Using the database that has been created by Analysis &
Synthesis, the Fitter matches the logic and timing requirements of the project
with the available resources of a device. It assigns each logic function to the
best logic cell location for routing and timing, and selects appropriate
interconnection paths and pin assignments. Figure 1 shows the place and
route design flow.
Figure 1. Place and Route Design Flow
If you have made resource assignments in your design, the Fitter attempts to
match those resource assignments with the resources on the device, tries to
meet any other constraints you may have set, and then attempts to optimize
the remaining logic in the design. If you have not set any constraints on the
design, the Fitter automatically optimizes it. If it cannot find a fit, the Fitter
terminates compilation and issues an error message.
In the Compilation Process Settings page of the Settings dialog box
(Assignments menu), you can specify whether you want to use a normal
compilation or smart compilation. With a “smart” compilation, the
Compiler creates a detailed database that can help future compilations run
faster, but may consume extra disk space. During a recompilation after a
smart compilation, the Compiler evaluates the changes made to the current
design since the last compilation and then runs only the Compiler modules
that are required to process those changes. If you make any changes to the
Quartus II Fitter
quartus_fit
Quartus II
Design Assistant
quartus_drc
to Quartus II
Timing Analyzer,
Simulator, EDA
Netlist Writer, or
Assembler
Quartus II
Settings
Files (.qsf)
Compiler
Database
Files (.cdb)
from Quartus II
Analysis &
Synthesis
Report Files
(.rpt, .htm)