Specifications

CHAPTER 4: SYNTHESIS
CONTROLLING ANALYSIS & SYNTHESIS
78 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Using Quartus II Synthesis Netlist
Optimization Options
Quartus II synthesis optimization options allow you to set options for
optimizing the netlist during synthesis for many of the Altera device
families. These optimization options are in addition to the optimization that
occurs during a standard compilation, and occur during the Analysis &
Synthesis stage of a full compilation. These optimizations make changes to
your synthesis netlist that are generally beneficial for area and speed. The
Synthesis Netlist Optimizations page under Analysis & Synthesis
Settings in the Settings dialog box (Assignments menu) allows you to
specify netlist optimization options, which include the following synthesis
optimization options:
■ Perform WYSIWYG primitive resynthesis
■ Perform gate-level register retiming
■ Allow register retiming to trade off Tsu/Tco with Fmax
For more information about synthesis netlist optimization options, refer to
“Using Netlist Optimizations to Achieve Timing Closure” on page 167 in
Chapter 9, “Timing Closure.”
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For Information About Refer To
Using Quartus II logic options to
control synthesis
“Logic Options,” “Creating, Editing, and
Deleting Assignments,” and “Specifying
Settings for Default Logic Options” in
Quartus II Help
Creating a logic option assignment Compilation module in the Quartus II
Tutorial
Using Quartus II synthesis options and
logic options that affect synthesis
“Quartus II Integrated Synthesis,” in the
Quartus II Handbook, vol. 1, on the Altera
web site
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For Information About Refer To
Using Quartus II synthesis and netlist
optimization options
“Netlist Optimizations & Physical Synthesis”
and “Design Optimization for Altera
Devices” in the Quartus II Handbook, vol. 2
on the Altera web site.