Specifications

CHAPTER 4: SYNTHESIS
USING QUARTUS II VERILOG HDL & VHDL INTEGRATED SYNTHESIS
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 71
“Instantiating Megafunctions in the Quartus II Software” on page 50 and
“Instantiating Megafunctions in EDA Tools” on page 52 in Chapter 2,
“Design Entry.”
When you create your Verilog HDL and VHDL designs, you should add
them to the project. You can add the design files when creating a project by
using the New Project Wizard (File menu), or by using the Files page of the
Settings dialog box, or, if you edit the files in the Quartus II Text Editor, you
are prompted to add the file to the current project when you save it. When
you add files to the project, you should make sure you add them in the order
you want Integrated Synthesis to process them. In addition, if you are using
VHDL designs, you can specify the VHDL library for the design in the
Properties dialog box that is available from the Files page. If you do not
specify a VHDL library, Analysis & Synthesis will compile VHDL entities
into the work library. For more information about adding files to a project,
refer to “Creating a Design” on page 43 in Chapter 2, “Design Entry.”
Analysis & Synthesis builds a single project database that integrates all the
design files in a design entity or project hierarchy. The Quartus II software
uses this database for the remainder of project processing. Other Compiler
modules update the database until it contains the fully optimized project. In
the beginning, the database contains only the original netlists; at the end, it
contains a fully optimized, fitted project, which is used to create one or more
files for timing simulation, timing analysis, device programming, and so on.
As it creates the database, the Analysis stage of Analysis & Synthesis
examines the logical completeness and consistency of the project, and checks
for boundary connectivity and syntax errors.
Analysis & Synthesis also synthesizes and performs technology mapping on
the logic in the design entity or project’s files. It infers flipflops, latches, and
state machines from Verilog HDL and VHDL. It creates state assignments
for state machines and makes choices that will minimize the number of
resources used. In addition, it replaces operators, such as + or - with
modules from the Altera library of parameterized modules (LPM) functions,
which are optimized for Altera devices.
Analysis & Synthesis uses several algorithms to minimize gate count,
remove redundant logic, and utilize the device architecture as efficiently as
possible. You can customize synthesis by using logic option assignments.
Analysis & Synthesis also applies logic synthesis techniques to help
implement timing requirements for a project and optimize the design to
meet these requirements.