Specifications

ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ IX
Preface
The Altera
®
Quartus
®
II design software is the most comprehensive
environment available for system-on-a-programmable-chip (SOPC) design.
If you have primarily used the MAX+PLUS
®
II software, other design
software, or ASIC design software in the past, and are thinking of making
the switch to the Quartus II software, or if you are somewhat familiar with
the Quartus II software but would like to gain a greater knowledge of its
capabilities, this manual is for you.
This manual is designed for the novice Quartus II software user and
provides an overview of the capabilities of the Quartus II software in
programmable logic design. It is not, however, intended to be an exhaustive
reference manual for the Quartus II software. Instead, it is a guide that
explains the features of the software and how these can assist you in FPGA
and CPLD design. This manual is organized into a series of specific
programmable logic design tasks. Whether you use the Quartus II graphical
user interface, other EDA tools, or the Quartus II command-line interface,
this manual guides you through the features that are best suited to your
design flow.
The first chapter gives an overview of the major graphical user interface,
EDA tool, and command-line interface design flows. Each subsequent
chapter begins with an introduction to the specific purpose of the chapter,
and leads you through an overview of each task flow. It shows how to
integrate the Quartus II software with your existing EDA tool and
command-line design flows. In addition, the manual refers you to other
resources that are available to help you use the Quartus II software, such as
Quartus II online Help and the Quartus II online tutorial, application notes,
white papers, and other documents and resources that are available on the
Altera web site.
Follow this manual through a tour of the Quartus II software to learn how it
can help you increase productivity and shorten design cycles, integrate with
existing programmable logic design flows, and achieve design,
performance, and timing requirements quickly and efficiently.