Specifications

CHAPTER 4: SYNTHESIS
USING QUARTUS II VERILOG HDL & VHDL INTEGRATED SYNTHESIS
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 69
Using Quartus II Verilog HDL &
VHDL Integrated Synthesis
You can use Analysis & Synthesis to analyze and synthesize Verilog HDL
and VHDL designs. Analysis & Synthesis includes Quartus II Integrated
Synthesis, which fully supports the Verilog HDL and VHDL languages and
provides options to control the synthesis process.
Analysis & Synthesis supports the Verilog-1995 (IEEE Std. 1364-1995) and
Verilog-2001 (IEEE Std. 1364-2001) standards, and also supports the VHDL
1987 (IEEE Std. 1076-1987) and 1993 (IEEE Std. 1076-1993) standards. You
can select which standard to use; Analysis & Synthesis uses Verilog-2001
and VHDL 1993 by default. If you are using another EDA synthesis tool, you
can also specify a Library Mapping File (.lmf) that the Quartus II software
should use to map non–Quartus II functions to Quartus II functions. You
can specify these and other options in the Verilog HDL Input and VHDL
Input pages, which are under Analysis & Synthesis Settings in the Settings
dialog box (Assignments menu). These pages are shown in Figure 2.
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Using the quartus_map executable
You can also run Analysis & Synthesis separately at the command prompt or in a
script by using the quartus_map executable. The quartus_map executable will
create a new project if it does not already exist.
The quartus_map executable creates a separate text-based report file that can be
viewed with any text editor.
If you want to get help on the quartus_map executable, type one of the following
commands at the command prompt:
quartus_map -h
r
quartus_map --help r
quartus_map --help=<topic name> r