Specifications

CHAPTER 4: SYNTHESIS
INTRODUCTION
68 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Introduction
You can use the Quartus
®
II Analysis & Synthesis module of the Compiler to
analyze your design files and create the project database. Analysis &
Synthesis uses Quartus II Integrated Synthesis to synthesize your Verilog
Design Files (.v) or VHDL Design Files (.vhd). If you prefer, you can use
other EDA synthesis tools to synthesize your Verilog HDL or VHDL design
files, and then generate an EDIF netlist file (.edf) or a Verilog Quartus
Mapping File (.vqm) that can be used with the Quartus II software. Figure 1
shows the synthesis design flow.
Figure 1. Synthesis Design Flow
You can start a full compilation in the Quartus II software, which includes
the Analysis & Synthesis module, or you can start Analysis & Synthesis
separately. The Quartus II software also allows you to perform an
Analysis & Elaboration to check a design for syntax errors without
performing a complete Analysis & Synthesis.
For more information about starting a full compilation or starting Compiler
modules individually, refer to “Graphical User Interface Design Flow” on
page 3 and “Command-Line Design Flow” on page 16 in Chapter 1, “Design
Flow.”
Quartus II Analysis &
Synthesis
quartus_map
Quartus II
Design Assistant
quartus_drc
to Quartus II
Fitter
EDA Synthesis
Tools
Verilog HDL &
VHDL source design
files (.v, .vhd)
EDIF netlist files (.edf) &
Verilog Quartus Mapping
Files (.vqm)
VHDL Design Files (.vhd),
Verilog HDL Design Files (.v),
Text Design Files (.tdf) & Block
Design Files (.bdf)
Compiler Database
Files (.rdb) & Report
Files (.rpt, .htm)
Library Mapping
Files (.lmf) &
User Libraries
Quartus II
RTL Viewer
Quartus II
Technology
Map Viewer