Specifications

CHAPTER 3: CONSTRAINT ENTRY

USING THE SETTINGS DIALOG BOX

60 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION

or more pins from the Unassigned Pins table to available pin or I/O bank

locations in the package diagram. In the Assigned Pins table, you can filter

the node names, change the I/O standards, and specify options for reserved

pins. In the Unassigned Pins table, you can change the node name and

direction for user-added nodes. You can also specify options for reserved

pins. If you want, you can also turn off the lists of assigned and unassigned

pins.

In the Pin Planner window, you can adjust the view and zoom in and out.

You can choose whether to display I/O banks, VREF groups, assignable

I/O pins, or differential pin pair connections. You can also display the

properties and available resources for the selected pin, and can display a

legend that explains the different colors and symbols that are used in the Pin

Planner.

Using the Settings Dialog Box

You can use the Settings dialog box (Assignments menu) to specify

assignments and options for your project. You can set general project-wide

options and synthesis, fitting, simulation, and timing analysis options.

Using the Settings dialog box, you can perform the following types of tasks:

■ Modify project settings: specify and view the current top-level entity

for project and revision information; add and remove files from the

project; specify custom user libraries; specify device options for

package, pin count, and speed grade; and specify migration devices.

■ Specify EDA tool settings: specify EDA tools for design entry/

synthesis, simulation, timing analysis, board-level verification, formal

verification, physical synthesis, and related tool options.

■ Specify Analysis & Synthesis settings: project-wide settings for

Analysis & Synthesis, Verilog HDL and VHDL input settings, default

design parameters, and synthesis netlist optimizations options.

For Information About Refer To

Using the Pin Planner to assign pins “I/O Planning using the Pin Planner,” in the

Quartus II Handbook, vol. 2, on the Altera

web site