Specifications

TABLE OF CONTENTS
VI ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Specifying Power Analyzer Options .........................................................................176
Using the PowerPlay Early Power Estimator...........................................................178
Chapter 11: Programming & Configuration ...........................................................................181
Introduction...................................................................................................................182
Programming One or More Devices by Using the Programmer...........................186
Creating Secondary Programming Files ...................................................................187
Creating Other Programming File Formats ...............................................188
Converting Programming Files....................................................................190
Using the Quartus II Software to Program Via a Remote JTAG Server................194
Chapter 12: Debugging ..............................................................................................................195
Introduction...................................................................................................................196
Using the SignalTap II Logic Analyzer......................................................................197
Setting Up & Running the SignalTap II Logic Analyzer ..........................198
Using the SignalTap II Logic Analyzer with Incremental Compilation. 202
Analyzing SignalTap II Data.........................................................................203
Using SignalProbe ........................................................................................................205
Using the In-System Memory Content Editor..........................................................208
Using the RTL Viewer & Technology Map Viewer..................................................210
Using the Chip Editor .................................................................................................. 211
Chapter 13: Engineering Change Management .....................................................................213
Introduction...................................................................................................................214
Identifying Delays & Critical Paths by Using the Chip Editor..............................215
Editing Atoms in the Chip Editor ..............................................................................217
Modifying Resource Properties by Using the Resource Property Editor.............217
Viewing & Managing Changes with the Change Manager....................................219
Verifying the Effect of ECO Changes.........................................................................221
Chapter 14: Formal Verification................................................................................................223
Introduction...................................................................................................................224
Using EDA Formal Verification Tools........................................................................225
Specifying Additional Settings ...................................................................................227
Chapter 15: System-Level Design.............................................................................................229
Introduction...................................................................................................................230
Creating SOPC Designs with SOPC Builder ............................................................232
Creating the System .......................................................................................232
Generating the System...................................................................................233
Creating DSP Designs with the DSP Builder............................................................234
Instantiating Functions..................................................................................235
Generating Simulation Files .........................................................................235
Generating Synthesis Files............................................................................235