Specifications

CHAPTER 2: DESIGN ENTRY
CREATING A DESIGN
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 43
Creating a Design
You can use the Quartus II software to create a design in the Quartus II Block
Editor or use the Quartus II Text Editor to create an HDL design using the
AHDL, Verilog HDL, or VHDL design languages.
The Quartus II software also supports designs created from EDIF Input
Files (.edf) or Verilog Quartus Mapping Files (.vqm) generated by EDA
design entry and synthesis tools. You can also create Verilog HDL or VHDL
designs in EDA design entry tools, and either generate EDIF Input Files and
VQM Files, or use the Verilog HDL or VHDL design files directly in
Quartus II projects. For more information on using EDA synthesis tools to
generate EDIF Input Files or VQM Files, see “Using Other EDA Synthesis
Tools” on page 72 in Chapter 4, “Synthesis.”
You can use the design file types listed in Table 2 to create a design in the
Quartus II software or in EDA design entry tools.
Table 2. Supported Design File Types
Type Description Extension
Block Design File A schematic design file created with the
Quartus II Block Editor.
.bdf
EDIF Input File An EDIF version 2 0 0 netlist file,
generated by any standard EDIF netlist
writer.
.edf
.edif
Graphic Design File A schematic design file created with the
MAX+PLUS II Graphic Editor.
.gdf
Text Design File A design file written in the Altera
Hardware Description Language (AHDL).
.tdf
Verilog Design File A design file that contains design logic
defined with Verilog HDL.
.v
.vlg
.verilog
VHDL Design File A design file that contains design logic
defined with VHDL.
.vh
.vhd
.vhdl
Verilog Quartus
Mapping File
A Verilog HDL–format netlist file
generated by the Synplicity Synplify
software or the Quartus II software.
.vqm