Specifications

CHAPTER 1: DESIGN FLOW
DESIGN METHODOLOGIES & DESIGN PLANNING
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 31
In the incremental compilation flow, you assign an instance of a design
entity to a design partition. You then assign the partitions to a physical
location on the device by using the Timing Closure Floorplan and the
LogicLock feature, and perform a full compilation of the design. During
compilation, the Compiler saves synthesis and fitting results in the project
database. After the first compilation, if you make additional changes to the
design, only the partitions that have changed require recompilation. When
you have finished making design changes, all the partitions are merged
together to allow you to perform a complete compilation. You can specify
whether you want to perform only an incremental synthesis, which can
reduce compilation time, or a full incremental compilation, which can
preserve performance in addition to significantly reducing compilation
time.
Since the incremental compilation flow prevents the Compiler from
optimizing across design partition boundaries, the Compiler may not be
able to perform as many optimizations for area and timing as would be
possible with regular compilation. To obtain best results for area and timing,
Altera recommends that you register the inputs and outputs of design
partitions, try to keep the number of design partitions to a reasonable
amount, avoid having too many critical paths that go beyond partition
boundaries, and avoid having partitions that are too small, such as smaller
than 1000 logic elements or Adaptive Logic Modules (ALMs).
For more information on assigning partitions and other stages of the
incremental compilation flow, see the following sections:
■ “Assigning Design Partitions” on page 62 in Chapter 3, “Constraint
Entry.”
■ “Performing Incremental Synthesis” on page 86 in Chapter 4,
“Synthesis.”
■ “Performing a Full Incremental Compilation” on page 92 in Chapter 5,
“Place & Route.”
■ “Using LogicLock Regions in Top-Down Incremental Compilation
Flows” on page 119 in Chapter 6, “Block-Based Design.”
■ “Using Incremental Compilation to Achieve Timing Closure” on page
172 in Chapter 9, “Timing Closure.”
■ “Using the SignalTap II Logic Analyzer with Incremental Compilation”
on page 202 in Chapter 12, “Debugging.”