Specifications

TABLE OF CONTENTS
IV ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Assigning Design Partitions in the Project Navigator ................................62
Assigning Design Partitions with the Design Partitions Window............63
Importing Assignments .................................................................................................64
Verifying Pin Assignments............................................................................................65
Chapter 4: Synthesis ..................................................................................................................... 67
Introduction..................................................................................................................... 68
Using Quartus II Verilog HDL & VHDL Integrated Synthesis................................69
Using Other EDA Synthesis Tools................................................................................72
Controlling Analysis & Synthesis ................................................................................75
Using Compiler Directives and Attributes...................................................75
Using Quartus II Logic Options.....................................................................76
Using Quartus II Synthesis Netlist Optimization Options ........................ 78
Using the Design Assistant to Check Design Reliability ..........................................79
Analyzing Synthesis Results with the RTL Viewer ................................................... 80
Analyzing Synthesis Results with the Technology Map Viewer .............................84
Performing Incremental Synthesis............................................................................... 86
Chapter 5: Place & Route.............................................................................................................89
Introduction..................................................................................................................... 90
Performing a Full Incremental Compilation .............................................................. 92
Analyzing Fitting Results.............................................................................................. 93
Using the Messages Window to View Fitting Results ................................93
Using the Report Window or Report File to View Fitting Results............95
Using the Timing Closure Floorplan to Analyze Results........................... 96
Using the Design Assistant to Check Design Reliability............................ 98
Optimizing the Fit ..........................................................................................................99
Using Location Assignments..........................................................................99
Setting Options that Control Place & Route...............................................100
Setting Fitter Options ......................................................................100
Setting Physical Synthesis Optimization Options ......................101
Setting Individual Logic Options that Affect Fitting..................101
Using the Resource Optimization Advisor ................................................102
Using the Design Space Explorer.................................................................105
Preserving Assignments through Back-Annotation................................................109
Chapter 6: Block-Based Design................................................................................................. 113
Introduction................................................................................................................... 114
Quartus II Block-Based Design Flow......................................................................... 114
Using LogicLock Regions............................................................................................ 116
Using LogicLock Regions in Top-Down Incremental Compilation Flows........... 119
Saving Intermediate Synthesis Results for Bottom-Up LogicLock Flows............120
Back-Annotating LogicLock Region Assignments....................................122
Exporting & Importing LogicLock Assignments ......................................122
Using LogicLock with EDA Tools ..............................................................................124