Specifications

CHAPTER 1: DESIGN FLOW
COMMAND-LINE DESIGN FLOW
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 19
quartus_cdb Compiler
Database Interface
(including VQM
Writer)
Generates internal netlist files, including VQM
Files, for the Quartus II Compiler database so
they can be used for back-annotation and for the
LogicLock feature, and back-annotates device
and resource assignments to preserve the fit for
future compilations. Also imports and exports
version-compatible databases and merges
partitions. Either the Fitter or Analysis &
Synthesis must be run successfully before
running the Compiler Database Interface.
quartus_sim Simulator Performs functional or timing simulation on your
design. Analysis & Synthesis must be run before
performing a functional simulation. The Timing
Analyzer must be run before performing a
timing simulation.
quartus_pow Power Analyzer Analyzes and estimates total dynamic and static
power consumed by a design. Computes toggle
rates and static probabilities for output signals.
The Fitter must be run successfully before
running the PowerPlay Power Analyzer.
quartus_pgm Programmer Programs Altera devices.
quartus_cpf Convert
Programming Files
Converts programming files to secondary
programming file formats.
quartus_stp SignalTap II Logic
Analyzer
Sets up your SignalTap II File (.stp). When it is
run after the Assembler, the SignalTap II Logic
Analyzer captures signals from internal device
nodes while the device is running at speed.
quartus_swb Software Builder Processes a design for an Excalibur embedded
processor.
quartus_sh Tcl Shell Provides a Tcl scripting shell for the Quartus II
software.
Table 3. Command-Line Executables (Part 2 of 2)
Executable
Name
Title Function