Specifications

CHAPTER 1: DESIGN FLOW
COMMAND-LINE DESIGN FLOW
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 17
Figure 9. Command-Line Design Flow
Command-Line Executables
The Quartus II software includes separate executables for each stage of the
design flow. Each executable occupies memory only while it is being run.
You can use these executables with standard command-line commands and
scripts, with Tcl scripts, and in makefile scripts. See Table 3 for a list of all of
the available command-line executables.
Programmer
quartus_pgm
Timing Analyzer
quartus_tan
Analysis &
Synthesis
quartus_map
Design Assistant
quartus_drc
Quartus II Shell
quartus_sh
Convert
Programming Files
quartus_cpf
EDA Netlist Writer
quartus_eda
Compiler Database
quartus_cdb
Simulator
quartus_sim
The Quartus II Shell can be
used as a Tcl interpreter for
the Quartus II executables
Source design files, including Verilog Design Files
(.v), VHDL Design Files (.vhd), Verilog Quartus
Mapping Files (.vqm), Text Design Files (.tdf), Block
Design Files (.bdf) & EDIF netlist files (.edf)
Output files for EDA tools,
including Verilog Output
Files (.vo), VHDL Output
Files (.vho), VQM Files &
Standard Delay Format
Output Files (.sdo)
SignalTap II Logic
Analyzer
quartus_stp
Software Builder
quartus_swb
PowerPlay Power
Analyzer
quartus_pow
Fitter
quartus_fit
Assembler
quartus_asm