Specifications

INDEX
264 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
settings (continued)
SignalProbe 206
SignalTap II Logic Analyzer 198
, 202
Simulator 60
, 138
Software Builder 60
, 239, 241, 243, 244
synthesis optimization 78
, 167
Timing Analyzer 60
Verilog HDL input 69
VHDL input 69
Settings dialog box 60
, 99, 143
shell, Tcl scripting 19
Shop Altera web site 257
Signal Activity Files (.saf) 128
, 132, 174
SignalProbe feature 196
, 205
compilation 206
design flow 196
reserving pins 207
using 206
SignalProbe Settings page 206
SignalTap II Files (.stp) 198
SignalTap II Logic Analyzer 196
, 197
analyzing data 203
design flow 196
incremental routing 201
Instance Manager 200
mnemonic tables 204
quartus_stpw executable 18
setting up and running 198
stand-alone version 18
, 200
triggers 200
SignalTap II Logic Analyzer page 202
simulation
libraries 134
simulation flow 128
Simulation page 130
Simulator 136
specifying settings 60
using 136
simulator initialization files 240
Simulator page 136
Simulator Tool 139
Slave Binary Image File (.sbi) 241
SOFs 182
, 186, 187
Software Build Settings page 239
, 241, 243,
244
Software Builder 238
flash programming files 240
generating output files 239
makeprogfile utility 239
memory initialization data files 244
passive programming files 242
simulator initialization files 240
specifying settings 60
, 239
software development see Software Builder
SOPC Builder 230
creating designs 232
creating system 232
design flow 230
generating system 233
System Contents page 233
System Generation page 233
using 232
SRAM Object Files (.sof) 182
, 186, 187, 242
stand-alone Programmer 182
Standard Delay Format Output Files
(.sdo) 129
STAPL see Jam Files (.jam); Jam Byte-Code
Files (.jbc)
Start Early Timing Estimate command 150
Start EDA Netlist Writer command 131
,
158
Start EDA Synthesis command 74
Start I/O Assignment Analysis
command 65
Start Partition Merge command 87
Start SignalProbe Compilation
command 206
Start Software Build command 238
Start Timing Analyzer (Fast Timing
Model) command 148
Start Timing Analyzer command 148
State Machine Viewer 82
state machines, viewing 82
Support Center 252
Symbol Editor 45
Synopsys Design Constraints File
(.sdc) 159
synthesis
design flow 68
incremental 30
, 62