Specifications

CHAPTER 15: SYSTEM-LEVEL DESIGN
CREATING DSP DESIGNS WITH THE DSP BUILDER
236 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
You can use the automated flow to control the entire synthesis and
compilation flow from within the MATLAB/Simulink design environment.
The SignalCompiler block creates VHDL Design Files and Tcl scripts,
performs synthesis in the Quartus II, LeonardoSpectrum, or Synplify
software, compiles the design in the Quartus II software, and can also
optionally download the design to a DSP development board. You can
specify which synthesis tool to use for the design from within the Simulink
software.
In the manual flow, the SignalCompiler block generates VHDL Design Files
and Tcl scripts that you can then use to perform synthesis manually in an
EDA synthesis tool, or the Quartus II software, which allows you to specify
your own synthesis or compilation settings. When generating output files,
the SignalCompiler block maps each Altera DSP Builder block to the VHDL
library. MegaCore functions are treated as black boxes.
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For Information About Refer To
Using the DSP Builder DSP Builder User Guide on the Altera web
site