Specifications

CHAPTER 1: DESIGN FLOW
EDA TOOL DESIGN FLOW
14 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
The individual pages under EDA Tool Settings provide additional options
for each type of EDA tool.
The following steps describe the basic design flow for using other EDA tools
with the Quartus II software. Refer to Table 2 on page 12 for a list of the
supported EDA tools.
1. Create a new project and specify a target device or device family.
2. Create a Verilog HDL or VHDL design file by using a standard text
editor. If you want, instantiate functions from libraries, or use the
MegaWizard Plug-In Manager (Tools menu) to create custom
variations of megafunctions.
3. Synthesize your design by using one of the Quartus II–supported EDA
synthesis tools, and generate an EDIF netlist file (.edf) or a Verilog
Quartus Mapping File (.vqm).
4. (Optional) Perform functional simulation on your design by using one
of the Quartus II–supported simulation tools.
5. In the Quartus II Settings dialog box (Assignments menu), specify
which EDA design entry, synthesis, simulation, timing analysis, board-
level verification, formal verification, and physical synthesis tools you
are using with the Quartus II software, and specify additional options
for those tools.
6. Compile your design and perform place and route by using the
Quartus II software. You can perform a full compilation, or you can run
the Compiler modules individually:
a. Run Analysis & Synthesis to process your design and map the
functions in your design to the correct library module.
b. Run the Fitter to place and route your design.
c. Run the Timing Analyzer to perform timing analysis on your
design.
d. Run the EDA Netlist Writer to generate output files for use with
other EDA tools.
e. Run the Assembler to create programming files for your design.