Specifications

CHAPTER 15: SYSTEM-LEVEL DESIGN
CREATING DSP DESIGNS WITH THE DSP BUILDER
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 235
software design with a physical FPGA board implementing a portion of that
design. You define the contents and function of the FPGA by creating and
compiling a Quartus II project. A simple JTAG interface between Simulink
and the FPGA board links the two.
Instantiating Functions
You can combine existing MATLAB functions and Simulink blocks with
Altera DSP Builder blocks and MegaCore functions, including those that
support the OpenCore Plus hardware evaluation feature, to link system-
level design and implementation with DSP algorithm development.
To use MegaCore functions that support the OpenCore Plus feature in your
design, you must download them before running the MATLAB/Simulink
environment.
Generating Simulation Files
After verifying the design in the Simulink software, you can use the DSP
Builder SignalCompiler block to generate files for simulating the design in
EDA simulation tools.
The SignalCompiler block translates a DSP Builder Simulink model into a
VHDL or Verilog model and generates a Verilog HDL or VHDL test bench
file that imports the Simulink input stimuli. You can use the Tcl script for
automated simulation in the ModelSim software, or simulate in another
EDA simulation tool with the Verilog HDL or VHDL test bench file.
Generating Synthesis Files
DSP Builder provides two synthesis and compilation flows: automated and
manual. You can synthesize the design in the Quartus II software, the
Mentor Graphics LeonardoSpectrum software, or the Synplicity Synplify
software with the Tcl script generated by the DSP Builder SignalCompiler
block. If the DSP Builder design is the top-level design, you can use either
the automated or manual synthesis flows. If the DSP Builder design is not
the top-level design, you must use the manual synthesis flow.