Specifications

CHAPTER 15: SYSTEM-LEVEL DESIGN
CREATING DSP DESIGNS WITH THE DSP BUILDER
234 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
SOPC Builder can also create software development kit (SDK) software
components, such as header files, generic peripheral drivers, custom
software libraries, and OS/real-time operating system (RTOS kernels), to
provide a complete design environment when the system is generated.
For simulation, SOPC Builder creates a Mentor Graphics
®
ModelSim
®
simulation directory that contains a ModelSim project file, the simulation
data files for all memory components, macro files to provide setup
information, aliases, and an initial set of bus-interface waveforms. It also
creates a simulation test bench that instantiates the system module, drives
clock and reset inputs, and instantiates and connects simulation models.
A Tcl script that sets up all the files necessary for compilation of the system
in the Quartus II software is also generated.
Creating DSP Designs with the
DSP Builder
The DSP Builder shortens DSP design cycles by helping you create the
hardware representation of a DSP design in an algorithm-friendly
development environment. The DSP Builder allows system, algorithm, and
hardware designers to share a common development platform. The DSP
Builder is an optional software package available from Altera, and is also
included with DSP Development Kits.
The DSP Builder also provides support for system-level debugging using
the SignalTap
®
II block or the Hardware in the Loop (HIL) block. You can
synthesize, compile and download the design, and then perform debugging,
all through the MATLAB/Simulink interface. The Hardware in the Loop
block to your Simulink model allows you to co-simulate a Quartus
®
II
f
For Information About Refer To
Using SOPC Builder “SOPC Builder,” in the Quartus II Handbook,
vol. 4, on the Altera web site
Application Note 333 (Developing
Peripherals for SOPC Builder) on the Altera
web site
“Overview: Using SOPC Builder” in
Quartus II Help