Specifications

CHAPTER 15: SYSTEM-LEVEL DESIGN
CREATING SOPC DESIGNS WITH SOPC BUILDER
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 233
SOPC Builder can import or provide an interface to user-defined blocks of
logic. There are four mechanisms for using an SOPC Builder system with
user-defined logic: simple PIO connection, instantiation inside the system
module, bus interface to external logic, and publishing a local SOPC Builder
component.
SOPC Builder provides library components (modules) for download,
including processors, such as the Nios
®
II processor, a UART, a timer, a PIO,
an Avalon tri-state bridge, several simple memory interfaces, and OS/RTOS
kernels. In addition, you can choose from an array of MegaCore
®
functions,
including those that support the OpenCore
®
Plus hardware evaluation
feature.
You can use the System Contents page of SOPC Builder to define the
system. You can select library components in the module pool and display
the added components in the module table.
You can use the information in the module table of the System Contents
page or in a separate wizard to define the following component options:
■ System components and interfaces
■ Master and slave connections
■ System address map
■ System IRQ assignments
■ Arbitration priorities for shared slaves
■ Multiple master and slave clock domains
Generating the System
Each project in SOPC Builder contains a system description file (PTF File),
which contains all the settings, options, and parameters entered in the SOPC
Builder. In addition, each component has a corresponding PTF File. During
system generation, the SOPC Builder uses these files to generate the source
code, software components, and simulation files for the system.
Once system definition is complete, you can generate the system using the
System Generation page of SOPC Builder.
The SOPC Builder software automatically generates all necessary logic to
integrate processors, peripherals, memories, buses, arbitrators, IP functions,
and interfaces to logic and memory outside the system across multiple clock
domains; and creates HDL source code that binds the components together.