Specifications

CHAPTER 15: SYSTEM-LEVEL DESIGN
INTRODUCTION
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 231
Figure 2. DSP Builder Design Flow
Intellectual
property (IP)
Verilog design
files, VHDL
design files
(.v, .vhd) & Tcl
Script Files (.tcl)
Simulation test
benches & Tcl Script
Files
DSP block
ready for
SOPC
Builder
MATLAB/
Simulink
DSP Builder
EDA Synthesis
Tool
Quartus II
Analysis & Synthesis
quartus_map
Quartus II
Fitter
quartus_fit
ModelSim/
ModelSim-Altera
Software
SOPC
Builder
SignalCompiler
Quartus II Assembler
quartus_asm
Programmer
Object File
(.pof)
Altera Programming
Software and
Hardware
Quartus II
EDA Netlist Writer
quartus_eda
Other EDA
Simulation Tool
Quartus II Simulator
quartus_sim