Specifications

CHAPTER 15: SYSTEM-LEVEL DESIGN
INTRODUCTION
230 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Introduction
The Quartus
®
II software supports the SOPC Builder and DSP Builder
system-level design flows. System-level design flows allow engineers to
rapidly design and evaluate system-on-a-programmable-chip (SOPC)
architectures and design at a higher level of abstraction.
The SOPC Builder is an automated system development tool that
dramatically simplifies the task of creating high-performance SOPC designs.
The tool automates the system definition and integration phases of SOPC
development completely within the Quartus II software. The SOPC Builder
allows you to select system components, define and customize the system,
and generate and verify the system before integration. Figure 1 shows the
SOPC Builder design flow.
Figure 1. SOPC Builder Design Flow
The Altera
®
DSP Builder integrates high-level algorithm and HDL
development tools by combining the algorithm development, simulation,
and verification capabilities of the MathWorks MATLAB and Simulink
system-level design tools with VHDL synthesis and simulation tools and the
Quartus II software. Figure 2 on page 231 shows the DSP Builder design
flow.
Processors
Intellectual
property (IP)
OS/RTOS
SOPC Builder
System definition, customization,
and automatic system generation
Verilog & VHDL
design files
(.v, .vhd)
Simulation test
benches, ESS model
files & object code
compiled to
memory models
Header files, generic
peripheral drivers,
custom software libraries &
OS/RTOS kernels
Select components
System verification &
construction
Customize & Integrate