Specifications

CHAPTER 14: FORMAL VERIFICATION
USING EDA FORMAL VERIFICATION TOOLS
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 225
an EDA synthesis tool and the Verilog Output Files (.vo) generated by the
Quartus II software. For the Cadence Encounter Conformal software, the
Quartus II software also allows you to verify the logical equivalence
between RTL VHDL design files (.vhd) or Verilog HDL design files (.v) and
Quartus II–generated Verilog Output Files. Figure 2 shows which file types
are compared in formal verification.
Figure 2. File Types Compared in Formal Verification
Using EDA Formal Verification Tools
You can use EDA formal verification tools to perform formal verification on
your Quartus II designs. The formal verification software compares whether
or not the Quartus II software correctly interprets the logic in the VQM File
or the source VHDL or Verilog HDL design file during synthesis and fitting.
Table 1 shows the list of EDA formal verification tools that are supported by
the Quartus II software.
Verilog Quartus
Mapping
Files (.vqm)
Quartus II -generated
Verilog Output
Files (.vo)
COMPARED WITH
Gate-Level Formal Verification
RTL Verilog HDL or
VHDL source design
files (.v, .vhd)
COMPARED WITH
RTL-Level Formal Verification
(Supported for Cadence Encounter Conformal Only)
Quartus II -generated
Verilog Output
Files (.vo)