Specifications

CHAPTER 14: FORMAL VERIFICATION
INTRODUCTION
224 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Introduction
The Quartus II software allows you to use formal verification EDA tools to
verify the logical equivalence between source design files and Quartus II
output files. Figure 1 shows the formal verification flow.
Figure 1. Formal Verification Flow
The type of formal verification supported by the Quartus II software is
equivalence checking, which compares the functional equivalence of the
source design with the revised design by using mathematical techniques
rather than by performing simulation using test vectors. Equivalence
checking greatly decreases the time to verify the design. The Quartus II
software allows you to verify the logical equivalence between the
synthesized gate-level Verilog Quartus Mapping Files (.vqm) generated by
Quartus II Fitter
quartus_fit
Quartus II
Analysis & Synthesis
quartus_map
EDA Synthesis
Tools
RTL Verilog HDL or
VHDL source design
files (.v, .vhd)
Verilog
Quartus
Mapping
Files (.vqm)
EDA Formal
Verification Tool
Verilog
Output
Files (.vo)
Quartus II Formal
Verification Libraries
Quartus II
EDA Netlist Writer
quartus_eda
Tool-specific
formal
verification
scripts
Gate-level VQM Files
compared against Quartus II
Verilog Output Files (.vo)
RTL VHDL & Verilog HDL source
design files compared against
Verilog Output Files (.vo) (Cadence
Encounter Conformal Only)
Compared against VQM
Files or RTL source files