Specifications

CHAPTER 13: ENGINEERING CHANGE MANAGEMENT
IDENTIFYING DELAYS & CRITICAL PATHS BY USING THE CHIP EDITOR
216 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
The Chip Editor displays all the resources of the device, such as
interconnects and routing lines, logic array blocks (LABs), RAM blocks, DSP
blocks, I/Os, rows, columns, and the interfaces between blocks and
interconnects and other routing lines.
You can control the level of detail of the Chip Editor display by zooming in
and out, selecting specific paths you want to display, and displaying a
separate Bird’s Eye View window, which shows a full view of the chip, with
the portion shown in the regular window denoted by a "view-port"
rectangle. You can also set options that control the display of different
resources, as well as fan-in and fan-out, critical paths, delay estimates on
signals, and Fitter placements. You can then use this information to
determine which properties and settings you may want to edit in the
Resource Property Editor. You can select one or more resources in the Chip
Editor and choose Locate in Resource Property Editor (right button pop-up
menu) to open the Resource Property Editor and make edits to the
resource(s). Refer to “Modifying Resource Properties by
Using the Resource Property Editor” on page 217 for more information.
If you select multiple elements, the Selected Elements Window command
(right button pop-up menu) allows you to locate to the Resource Property
Editor or other editors, and allows you to remove elements from the
selection, if desired.
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For Information About Refer To
Engineering change management and
using the Chip Editor
“Engineering Change Management” in the
Quartus II Handbook, vol. 1, on the Altera
web site
“Design Analysis and Engineering Change
Management with the Chip Editor,” in the
Quartus II Handbook, vol. 3, on the Altera
web site
Using the Chip Editor “Overview: Using the Chip Editor” and
“Making Post-Compilation Changes
Introduction” in Quartus II Help