Specifications

CHAPTER 13: ENGINEERING CHANGE MANAGEMENT
IDENTIFYING DELAYS & CRITICAL PATHS BY USING THE CHIP EDITOR
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 215
7. Use the Check and Save All Netlist Changes command (Edit menu) to
check the legality of the change for all of the other resources in the
netlist.
8. Run the Assembler to generate a new programming file or run the EDA
Netlist Writer again to generate a new netlist. If you want to verify
timing changes, you can run the Timing Analyzer. If you want to verify
that simulations are correct, you can run the Simulator.
Identifying Delays & Critical Paths
by Using the Chip Editor
You can use the Chip Editor to view details of placement and routing. The
Chip Editor reveals additional details about design placement and routing
that are not visible in the Quartus II Timing Closure floorplan. It shows
complete routing information, showing all possible and used routing paths
between each device resource. See Figure 2.
Figure 2. Chip Editor
Displays fan-in and fan-out
connections of a selected resource
Shows routing
delays
Displays
resource usage