Specifications

CHAPTER 12: DEBUGGING

USING THE SIGNALTAP II LOGIC ANALYZER

ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 203

3. Create and open a SignalTap II File.

4. Turn on the Incremental Compile option in the SignalTap II Logic

Analyzer Instance Manager next to the instance you want to compile

incrementally (see Figure 3 on page 199).

When you use incremental compilation, you must use post-fitting

SignalTap II nodes; if the nodes are not post-fitting nodes, the

SignalTap II Logic Analyzer converts them to post-fitting nodes when

you turn on the Incremental Compile option.

5. Run the SignalTap II Logic Analyzer. For the instances that are in

incremental mode, any changes will be compiled incrementally,

without requiring a full project compilation

For more information about incremental compilation, refer to “Top-Down

Incremental Compilation Flow” on page 30 in Chapter 1, “Design Flow.” and

“Performing a Full Incremental Compilation” on page 92 in Chapter 5,

“Place & Route.”

Analyzing SignalTap II Data

When you use the SignalTap II Logic Analyzer to view the results of a logic

analysis, the data is stored in the internal memory on the device and then

streamed to the waveform view in the logic analyzer, via the JTAG port.

In the waveform view, you can insert time bars, align node names, and

duplicate nodes; create, rename, and ungroup a bus; specify a data format

for bus values; and print the waveform data. The data log that is used to

create the waveform shows a history of data that is acquired with the

SignalTap II Logic Analyzer. The data is organized in a hierarchical manner;

logs of captured data using the same trigger are grouped together in Trigger

Sets. Figure 5 shows the waveform view.

For Information About Refer To

Using Quartus II incremental

compilation

“Quartus II Incremental Compilation,” in the

Quartus II Handbook, vol. 1, on the Altera

web site

“Overview: Using Incremental Compilation”

in Quartus II Help