Specifications

CHAPTER 12: DEBUGGING
USING THE SIGNALTAP II LOGIC ANALYZER
202 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
incremental routing is used, in the SignalTap II Logic Analyzer page
of the Settings dialog box (Assignments menu). Also, you must reserve
trigger or data nodes for SignalTap II incremental routing using the
Trigger Nodes allocated and Data Nodes allocated boxes before
compiling the design. You can find nodes for SignalTap II incremental
routing sources by selecting SignalTap II: post-fitting in the Filter list
in the Node Finder.
Incremental routing can be used when the design is not incremental
compilation mode. If you want to analyze post-fitting nodes without
performing a full recompilation when the project is in incremental
compilation mode, you should use SignalTap II incremental
compilation instead. For more information, refer to the next section,
“Using the SignalTap II Logic Analyzer with Incremental
Compilation.”
■ Attach Programming File: Allows you to have multiple SignalTap II
configurations (trigger setups) and the associated programming files in
a single SignalTap II File. You can use the SOF Manager to add, rename,
or remove SRAM Object Files (.sof), extract SOFs from the SignalTap II
File, or program the device.
Using the SignalTap II Logic Analyzer
with Incremental Compilation
The incremental compilation feature helps to shorten the debugging process
time considerably by allowing you to analyze post-fitting nodes
incrementally with the SignalTap II Logic Analyzer without performing a
full compilation of the design.
Unlike the incremental fitting feature, the incremental compilation feature
does not require you to perform a smart compilation, and it can be used in
incremental compilation mode.
The following steps describe the basic flow for performing a SignalTap II
logic analysis with incremental compilation:
1. Make sure that the Full incremental compilation option is turned on in
the Compilation Process Settings page of the Settings dialog box
(Assignments menu).
2. Remove all design partition assignments.