Specifications

CHAPTER 12: DEBUGGING
INTRODUCTION
196 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Introduction
The Quartus
®
II SignalTap
®
II Logic Analyzer and the SignalProbe
™
feature
analyze internal device nodes and I/O pins while operating in-system and
at system speeds. The SignalTap II Logic Analyzer uses an embedded logic
analyzer to route the signal data through the JTAG port to either the
SignalTap II Logic Analyzer or an external logic analyzer or oscilloscope,
based on user-defined trigger conditions. You can also use a stand-alone
version of the SignalTap II Logic Analyzer to capture signals. The
SignalProbe feature uses incremental routing on unused device routing
resources to route selected signals to an external logic analyzer or
oscilloscope. Figure 1 and Figure 2 show the SignalTap II and SignalProbe
debugging flows.
Figure 1. SignalTap II Debugging Flow
Programming
Files
Quartus II Fitter
quartus_fit
Quartus II Assembler
quartus_asm
Quartus II
Programmer
quartus_pgm
Altera Device
SignalTap II
Logic Analyzer
External Logic
Analyzer or
Oscilloscope
SignalTap II
File (.stp)
Quartus II
Analysis & Synthesis
quartus_map
Partition Merge
quartus_cdb
-- merge
for SignalTap incremental compilation flow
for standard
SignalTap flow