Specifications

CHAPTER 1: DESIGN FLOW
EDA TOOL DESIGN FLOW
10 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
9. (Optional) Perform functional simulation on the design by using the
Simulator and the Generate Functional Simulation Netlist command.
10. Perform place and route on the design by using the Fitter.
11. Perform a power estimation and analysis by using the PowerPlay
Power Analyzer.
12. Perform timing analysis on the design by using the Timing Analyzer.
13. Perform timing simulation on the design by using the Simulator.
14. (Optional) Make timing improvements to achieve timing closure by
using physical synthesis, the Timing Closure floorplan, the LogicLock
feature, the Settings dialog box, and the Assignment Editor.
15. Create programming files for your design by using the Assembler.
16. Program the device by using programming files, the Programmer, and
Altera hardware; or convert programming files to other file formats for
use by other systems, such as embedded processors.
17. (Optional) Debug the design by using the SignalTap
®
II Logic Analyzer,
the SignalProbe
™
feature, or the Chip Editor.
18. (Optional) Manage engineering changes by using the Chip Editor, the
Resource Property Editor, and the Change Manager.
EDA Tool Design Flow
The Quartus II software allows you to use the EDA tools you are familiar
with for various stages of the design flow. You can use these tools together
with the Quartus II graphical user interface or with Quartus II command-
line executables. Figure 7 shows the EDA tool design flow.