Specifications

CHAPTER 9: TIMING CLOSURE

USING LOGICLOCK REGIONS TO ACHIEVE TIMING CLOSURE

ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 169

Netlist optimizations for physical synthesis and fitting include the following

options:

■ Perform physical synthesis for combinational logic: Directs the

Quartus II software to try to increase performance by performing

physical synthesis optimizations on combinational logic during fitting.

■ Perform register duplication: Directs the Quartus II software to

increase performance by using register duplication to perform physical

synthesis optimizations on registers during fitting.

■ Perform register retiming: Directs the Quartus II software to increase

performance by using register retiming to perform physical synthesis

optimizations on registers during fitting.

■ Physical synthesis effort: Specifies the level of effort used by the

Quartus II software when performing physical synthesis (Normal,

Extra, and Fast).

The Quartus II software cannot perform these netlist optimizations for

fitting and physical synthesis on a back-annotated design. In addition, if you

use one or more of these netlist optimizations on a design, and then back-

annotate the design, you must generate a Verilog Quartus Mapping

File (.vqm) if you wish to save the results. The VQM File must be used in

place of the original design source code in future compilations.

Using LogicLock Regions to Achieve

Timing Closure

You can use LogicLock regions to achieve timing closure by analyzing the

design in the Timing Closure floorplan, and then constraining critical logic

in LogicLock regions. LogicLock regions are generally hierarchical, giving

you more control over the placement and performance of modules or groups

For Information About Refer To

Achieving timing closure using netlist

optimizations

“Netlist Optimizations and Physical

Synthesis,” in the Quartus II Handbook, vol.

2, on the Altera web site