Specifications

CHAPTER 9: TIMING CLOSURE
USING NETLIST OPTIMIZATIONS TO ACHIEVE TIMING CLOSURE
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 167
The Timing Optimization Advisor features are very similar to the Resource
Optimization Advisor; for more information, refer to “Using the Resource
Optimization Advisor” on page 102 in Chapter 5, “Place & Route.”
Using Netlist Optimizations to
Achieve Timing Closure
The Quartus II software includes netlist optimization options to further
optimize your design during synthesis and during place and route. Netlist
optimizations are push-button features that offer improvements to f
MAX
results by making modifications to the netlist to improve performance.
These options can be applied regardless of the synthesis tool used.
Depending on your design, some options may have more of an effect than
others.
You can specify synthesis and physical synthesis netlist optimizations in the
Synthesis Netlist Optimizations and Physical Synthesis Optimizations
pages of the Settings dialog box (Assignments menu). See Figure 4 on
page 168.
Netlist optimizations for synthesis include the following options:
■ Perform WYSIWYG primitive resynthesis: Directs the Quartus II
software to unmap WYSIWYG primitives during synthesis. When this
option is turned on, the Quartus II software unmaps the logic elements
in an atom netlist to gates and remaps the gates to Altera
®
LCELL
primitives. This option allows the Quartus II software to use different
techniques specific to a device architecture during the remapping
process and uses the optimization technique (Area, Balanced, or
Speed) that you specified in the Analysis & Synthesis Settings page of
the Settings dialog box.
■ Perform gate-level register retiming: Allows registers to be moved
across combinational logic to balance timing, but does not change the
functionality of the current design. This option moves registers across
combinational gates only, and not across user-instantiated logic cells,
memory blocks, DSP blocks, or carry or cascade chains, and has the
ability to move registers from the inputs of a combinational logic block
to the block’s output, potentially combining the registers. It can also
create multiple registers at the input of a combinational logic block
from a register at the output of a combinational logic block.