Specifications

CHAPTER 9: TIMING CLOSURE

USING THE TIMING CLOSURE FLOORPLAN

164 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION

potential destination resources (the darker the resource, the longer the

delay) and the delay to a destination resource is shown numerically by

placing the mouse over another physical resource.

■ Routing congestion: displays a graphical representation of the routing

congestion in a design. The darker the shading, the greater the routing

resource utilization. You can select a routing resource and then specify

the congestion threshold (displayed as red areas in the device) for the

resource.

■ Critical paths: displays the critical paths in a design, including path

edges and routing delays. The default critical path view shows the

nodes for the worst-case path between the source and destination

nodes. You can specify criteria for filtering which critical paths are

displayed by specifying the clock domain, source and destination node

names, the number of critical paths to display, and slack.

You can also view the routing information for LogicLock regions in the

design, including connectivity and intra-region delay. LogicLock region

connectivity displays the connectivity between entities assigned to

LogicLock regions in the design and intra-region delay displays the

maximum time delay between source and destination paths in a LogicLock

region, including its child regions.

The Equations window displays routing and equation information for pin,

I/O cell, logic cell, and embedded cell assignments. When you turn on

Equations (View menu), the Equations window is displayed at the bottom

of the Timing Closure floorplan window. See Figure 2.

Figure 2. Equations Window

By selecting one or more logic cell, embedded cell, and/or pin assignments

in the floorplan, you can display their equations, fan-in, and fan-out in the

Equations list and expand or collapse the terms. The Fan-In list displays all