Specifications

CHAPTER 8: TIMING ANALYSIS
PERFORMING TIMING ANALYSIS BY USING EDA TOOLS
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 159
Using the PrimeTime Software
The Quartus II software generates a Verilog Output File or VHDL Output
File, a Standard Delay Format Output File (.sdo) that contains timing delay
information, and a Tcl Script File that sets up the PrimeTime environment.
If you are performing a minimum timing analysis, the Quartus II software
uses the minimum delay information generated by the Timing Analyzer in
the SDF Output File for the design.
Using the NativeLink feature, you can specify that the Quartus II software
launches the PrimeTime software in either command-line or GUI mode. You
can also specify a Synopsys Design Constraints File (.sdc) that contains
timing assignments for use in the PrimeTime software.
The following steps describe the basic flow to manually use the PrimeTime
software to perform timing analysis on a design after compilation in the
Quartus II software:
1. Specify EDA tool settings, either through the Settings dialog box
(Assignments menu), or during project setup, using the New Project
Wizard (File menu).
2. Compile your design in the Quartus II software to generate the output
netlist files. The Quartus II software places the files in a tool-specific
directory.
!
Using the quartus_eda executable
You can also run the EDA Netlist Writer to generate the necessary output files
separately at the command prompt or in a script by using the quartus_eda
executable. You must run the Quartus II Fitter executable quartus_fit before
running the EDA Netlist Writer.
The quartus_eda executable creates a separate text-based report file that can be
viewed with any text editor.
If you want to get help on the quartus_eda executable, type one of the following
commands at the command prompt:
quartus_eda -h
r
quartus_eda -help r
quartus_eda --help=<topic name> r