Specifications

CHAPTER 8: TIMING ANALYSIS
VIEWING TIMING ANALYSIS RESULTS
152 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Viewing Timing Analysis Results
After you run a timing analysis, you can view the timing analysis results or
early timing estimates in the Timing Analyzer folder of the Compilation
Report. You can then list the timing paths to validate circuit performance,
determine critical speed paths and paths that limit the design’s performance,
and make additional timing assignments. Additionally, you can use the
list_path Tcl command to locate and view information on any delay path
in the design.
You can also use the Timing Closure floorplan (Project menu) to view
information on the critical paths in the design and view routing congestion.
For more information on using the Timing Closure floorplan to view critical
paths and routing congestion, refer to “Using the Timing Closure Floorplan”
on page 162 in Chapter 9, “Timing Closure.”
If you are familiar with MAX+PLUS
®
II timing reporting, you can find
timing information, such as the delay information from the MAX+PLUS II
Delay Matrix, in the Timing Analyzer sections of the Compilation Report
and in the Custom Delays tab of the Timing Analyzer Tool window.
Using the Report Window
The Timing Analysis sections in the Report window list the reported timing
information for clock setup and clock hold; t
SU
, t
H
, t
PD
, and t
CO
; and
minimum t
PD
and t
CO
. The Timing Analysis Report window sections also
list maximum clock arrival skew, maximum data arrival skew, minimum
pulse width requirements; any timing assignments that were ignored
during the timing analysis; and any messages generated by the Timing
Analyzer.
The Report Window reports the following types of information for timing
analysis:
■ Settings for timing requirements
■ Slack and minimum slack
■ Source and destination clock names
■ Source and destination node names
■ Required and actual point-to-point times
■ Actual f
MAX