Specifications

CHAPTER 8: TIMING ANALYSIS
PERFORMING TIMING ANALYSIS IN THE QUARTUS II SOFTWARE
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 147
■ Clock uncertainty assignments: allow you to specify the expected
clock setup or hold uncertainty (jitter) that should be used when
performing setup and hold checks. The Timing Analyzer subtracts the
specified setup uncertainty from the data required time when
calculating setup checks and adds the specified hold uncertainty to the
data required time when calculating hold checks.
■ Clock latency assignments: allow you to specify additional early or
late clock delays as latencies. Latencies affect clock skew, which is
different from offsets, which affect the setup relationship. The clock
latency represents the external delay from a virtual (ideal) clock
through either the shortest path or the longest path. For setup analysis,
the Timing Analyzer uses the late latency value for each source and the
early latency value for each destination register, and for hold analysis,
the Timing Analyzer uses the early latency value for each source and
the late latency value for each destination register.
■ Multicycle paths: paths between registers that require more than one
clock cycle to become stable. You can set multicycle paths to instruct the
Timing Analyzer to relax its measurements and avoid incorrect setup
or hold time violations.
■ Cut paths: by default, the Quartus II software will cut paths between
unrelated clock domains when there are no timing requirements set or
only the default required f
MAX
clock setting is used. The Quartus II
software will also cut paths between unrelated clock domains if
individual clock assignments are set but there is no defined relationship
between the clock assignments. You can also define cut paths for
specific paths in the design.
■ Maximum delay requirements: requirements for input or output
maximum delay, or maximum timing requirements for t
SU
, t
H
, t
PD
, and
t
CO
on specific nodes in the design. You can make these assignments to
specific nodes or groups to override project-wide maximum timing
requirements.
■ Minimum delay requirements: requirements for input or output
minimum delay, or minimum timing requirements for t
H
, t
PD
, and t
CO
for specific nodes or groups. You can make these assignments to
specific nodes or groups to override project-wide minimum timing
requirements.
■ Maximum skew requirements: timing requirements for maximum
clock and data arrival skew for specific nodes or groups.