Specifications

CHAPTER 8: TIMING ANALYSIS
PERFORMING TIMING ANALYSIS IN THE QUARTUS II SOFTWARE
146 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Specifying Individual Timing Assignments
You can make individual timing assignments to individual entities, nodes,
and pins with the Assignment Editor. Individual timing assignments
override project-wide requirements (if they are more stringent). The
Assignment Editor supports point-to-point timing assignments, wildcards
to identify specific nodes when making assignments, and time group
assignments to make individual assignments to groups of nodes.
The timing requirements that you enter for pins and nodes are saved in the
Quartus II Settings File (.qsf) for the top-level entity in the current hierarchy.
You can make the following types of individual timing assignments in the
Timing Analyzer:
■ Individual clock settings: allow you to perform an accurate multiclock
timing analysis by defining the timing requirements and relationship of
all clock signals in the design. The Timing Analyzer supports both
single-clock and multiclock frequency analysis.
t
H
(clock hold time) The length of time for which data that feeds a register
via its data or enable input(s) must be retained at an
input pin after the clock signal that clocks the register is
asserted at the clock pin.
t
CO
(clock-to-output delay) The time required to obtain a valid output at an output
pin that is fed by a register after a clock signal transition
on an input pin that clocks the register.
t
PD
(pin to pin delay) The time required for a signal from an input pin to
propagate through combinational logic and appear at an
external output pin.
minimum t
CO
(clock-to-
output delay)
The minimum time required to obtain a valid output at
an output pin that is fed by a register after a clock signal
transition on an input pin that clocks the register. This
time always represents an external pin-to-pin delay.
minimum t
PD
(clock-to-
output delay)
Specifies the minimum acceptable pin-to-pin delay, that
is, the time required for a signal from an input pin to
propagate through combinational logic and appear at an
external output pin.
Table 1. Project-Wide Timing Settings (Part 2 of 2)
Requirement Description