Specifications

CHAPTER 8: TIMING ANALYSIS
PERFORMING TIMING ANALYSIS IN THE QUARTUS II SOFTWARE
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 145
You can specify I/O timing requirements by including these paths as part of
the clock analysis and using the Input Maximum Delay, Input Minimum
Delay, Output Maximum Delay, or Output Minimum Delay assignments
to specify delays based on external device timing, or you can specify I/O
timing by using the traditional t
SU
requirement, t
CO
requirement, and/or
t
H
requirement timing assignments. Both types of I/O timing requirements
ultimately produce similar results through different methods.
Using the Settings dialog box or the Timing wizard, you can specify the
following timing requirements and other options:
■ Overall frequency requirement for the project, or settings for individual
clock signals
■ Delay requirements, minimum delay requirements, and path-cutting
options
■ Reporting options, including the number of source and destination
registers and exclude paths
■ Timing-driven compilation options
■ Options for setup (recovery) and hold (removal) checks on timing paths
that have an asynchronous clear, preset, or load signal.
Specifying Project-Wide Timing Settings
Project-wide timing settings include maximum frequency, setup time, hold
time, clock-to-output delay and pin-to-pin delay, and minimum timing
requirements. You can also set project-wide clock settings and multiple
clock domains, and path-cutting options.
Table 1. Project-Wide Timing Settings (Part 1 of 2)
Requirement Description
f
MAX
(maximum frequency) The maximum clock frequency that can be achieved
without violating internal setup (t
SU
) and hold (t
H
) time
requirements.
t
SU
(clock setup time) The length of time for which data that feeds a register
via its data or enable input(s) must be present at an input
pin before the clock signal that clocks the register is
asserted at the clock pin.