Specifications

CHAPTER 8: TIMING ANALYSIS
PERFORMING TIMING ANALYSIS IN THE QUARTUS II SOFTWARE
144 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Figure 2. Timing Requirements & Options Page of Settings Dialog Box
You can make individual timing settings with the Assignment Editor. After
specifying project-wide timing assignments and/or individual timing
assignments, you can run a timing analysis by compiling the design, or by
running the Timing Analyzer separately after an initial compilation.
If you do not specify timing requirement settings or options, the Quartus II
Timing Analyzer will run the analyses using default settings. By default, the
Timing Analyzer calculates and reports the f
MAX
of every register-to-
register delay, the t
SU
and t
H
of every input register, the t
CO
of every output
register, the t
PD
between all pin-to-pin paths, hold times, minimum t
CO
, and
minimum t
PD
of the current design entity. Slack times are reported when
constraints are provided or when defaults are applicable.
Clicking the More Settings button displays the More Timing Settings
dialog box, which contains additional options