Specifications

CHAPTER 8: TIMING ANALYSIS
INTRODUCTION
142 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Introduction
The Quartus
®
II Timing Analyzer allows you to analyze the performance of
all logic in your design and helps to guide the Fitter to meet the timing
requirements in your design. By default, the Timing Analyzer runs
automatically as part of a full compilation to analyze and report timing
information such as the setup times (t
SU
), hold times (t
H
), clock-to-output
delays and minimum clock-to-output delays (t
CO
), pin-to-pin delays and
minimum pin-to-pin delays (t
PD
), maximum clock frequencies (f
MAX
), and
other timing characteristics for the design. The Timing Analyzer also reports
slack times when timing constraints are provided or when defaults are
applicable. You can use the information generated by the Timing Analyzer
to analyze, debug, and validate the timing performance of your design. You
can also perform timing analysis using fast timing models, to verify timing
under best-case (fastest delays of the fastest speed grade) conditions.
Figure 1 shows the timing analysis flow.
Figure 1. Timing Analysis Flow
from Quartus II
Fitter
Quartus II
Settings Dialog Box
Quartus II
Assignment Editor
Quartus II
EDA Netlist Writer
quartus_eda
EDA Board-Level
Analysis Tool
Synopsys
PrimeTime Software
Quartus II
Timing Analyzer
quartus_tan
from Quartus II
Fitter
Quartus II
Settings
File (.qsf)
Report
Files
(.rpt, .htm)
STAMP Model Files
(.data, .mod, or .lib)
Verilog Output Files (.vo),
VHDL Output Files (.vho),
Standard Delay Format
Output Files (.sdo) &
Tcl Script Files (.tcl)