Specifications

CHAPTER 7: SIMULATION
SIMULATING DESIGNS WITH EDA TOOLS
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 133
4. Compile the design files and test bench files with the EDA simulation
tool.
5. Perform the simulation with the EDA simulation tool.
NativeLink Simulation Flow
You can use the NativeLink feature to perform the steps to setup and run an
EDA simulation tool automatically from within the Quartus II software. The
following steps describe the basic flow for using EDA simulation tools with
the NativeLink feature:
1. Specify EDA tool settings in the Quartus II software, either through the
Settings dialog box (Assignments menu), or during project setup,
using the New Project Wizard (File menu).
2. Turn on Run this tool automatically after compilation when
specifying EDA tool settings.
3. Compile the design in the Quartus II software. The Quartus II software
performs the compilation, generates the Verilog HDL or VHDL output
files and corresponding SDF Output Files (if you are performing a
timing simulation), and launches the simulation tool. The Quartus II
software directs the simulation tool to create a working library; compile
or map to the appropriate libraries, design files, and test bench files; set
up the simulation environment; and run the simulation.
Manual Timing Simulation Flow
If you want more control over the simulation, you can generate the
Verilog HDL or VHDL output files and corresponding SDF Output File in
the Quartus II software, and then manually launch the simulation tool to
perform the simulation. The following steps describe the basic flow needed
to perform a timing simulation of a Quartus II design using an EDA
simulation tool. Refer to Quartus II Help for more information on specific
EDA simulation tools.
1. Specify EDA tool settings in the Quartus II software, either through the
Settings dialog box (Assignments menu), or during project setup,
using the New Project Wizard (File menu).