Specifications

CHAPTER 7: SIMULATION
SIMULATING DESIGNS WITH EDA TOOLS
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 129
Simulating Designs with EDA Tools
The EDA Netlist Writer module of the Quartus II software generates VHDL
Output Files (.vho) and Verilog Output Files (.vo) for performing functional
or timing simulation and Standard Delay Format Output Files (.sdo) that are
required for performing timing simulation with EDA simulation tools. The
Quartus II software generates SDF Output Files in Standard Delay Format
version 2.1. The EDA Netlist Writer places simulation output files in a tool-
specific directory under the current project directory.
In addition, the Quartus II software offers seamless integration for timing
simulation with EDA simulation tools through the NativeLink feature. The
NativeLink feature allows the Quartus II software to pass information to
EDA simulation tools, and includes the ability to launch EDA simulation
tools from within the Quartus II software.
Table 1 lists the EDA simulation tools that are supported by the Quartus II
software and indicates which tools support the NativeLink feature.
Table 1. Quartus II–Supported EDA Simulation Tools
Simulation
Tool Name
NativeLink
Support
Cadence Verilog-XL
Cadence NC-Verilog v
Cadence NC-VHDL v
Mentor Graphics
®
ModelSim
®
v
Mentor Graphics ModelSim-Altera v
Synopsys Scirocco v
Synopsys VCS MX v
Synopsys VCS v
Synopsys VSS
!
The ModelSim-Altera Software
The Mentor Graphics ModelSim-Altera software is included in Altera
®
design
software subscriptions for functional simulation and HDL test bench support.