Specifications

CHAPTER 7: SIMULATION
INTRODUCTION
128 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Introduction
You can perform functional and timing simulation of your design by using
EDA simulation tools or the Quartus
®
II Simulator.
The Quartus II software provides the following features for performing
simulation of designs in EDA simulation tools:
■ NativeLink
®
integration with EDA simulation tools
■ Generation of output netlist files
■ Functional and timing simulation libraries
■ Generation of test bench template and memory initialization files
■ Generation of Signal Activity Files (.saf)
Figure 1 shows the simulation flow with EDA simulation tools and the
Quartus II Simulator.
Figure 1. Simulation Flow
Quartus II
EDA Netlist Writer
quartus_eda
EDA
Simulation Tool
(Functional)
Functional
simulation
libraries
Quartus II Simulator
quartus_sim
EDA
Simulation Tool
(Timing)
Quartus II
Waveform Editor
Timing simulation
libraries
Verilog Output
Files, VHDL
Output Files &
test bench files
Test bench
files
Verilog Output Files (.vo),
VHDL Output Files (.vho),
Standard Delay Format
Output Files (.sdo) &
test bench files (.vt, .vht)
from Quartus II
Fitter
Waveform files
Signal
Activity
Files (.saf)