Specifications

CHAPTER 6: BLOCK-BASED DESIGN
SAVING INTERMEDIATE SYNTHESIS RESULTS FOR BOTTOM-UP LOGICLOCK FLOWS
122 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Back-Annotating LogicLock Region
Assignments
You can use the Back-Annotate Assignments (Advanced Type) command
to lock the logic placement into LogicLock regions in a design before
exporting the assignments for use in a top-level design. Back-annotation
allows you to maintain the performance of a LogicLock region when
importing the region and its assignments into a top-level design.
You must use the Back-Annotate Assignments (Advanced Type) command
to back-annotate LogicLock region assignments, and you can also use it to
back-annotate designs that do not include LogicLock region assignments.
For more information on back-annotating assignments, refer to “Preserving
Assignments through Back-Annotation” on page 109 in Chapter 5, “Place &
Route.”
Exporting & Importing LogicLock
Assignments
The Export Assignments and Import Assignments dialog boxes
(Assignments menu) allow you to optimize entities individually using
LogicLock region assignments and preserve your optimization when you
instantiate those entities in a top-level design.
When you export LogicLock region assignments, the Quartus II software
writes all LogicLock region assignments, other QSF assignments, and I/O
standard assignments that apply to the specific entity instance to a QSF that
you specify in the Export Assignments dialog box. By default, the Quartus II
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Using the quartus_cdb executable
You can also save intermediate synthesis results as a VQM File, back-annotate
assignments, and export and import LogicLock regions separately at the command
prompt or in a script by using the quartus_cdb executable.
If you want to get help on the quartus_cdb executable, type one of the following
commands at the command prompt:
quartus_cdb -h
r
quartus_cdb --help r
quartus_cdb --help=<topic name> r