Specifications

CHAPTER 6: BLOCK-BASED DESIGN
SAVING INTERMEDIATE SYNTHESIS RESULTS FOR BOTTOM-UP LOGICLOCK FLOWS
ALTERA CORPORATION INTRODUCTION TO QUARTUS II ■ 121
You can design a block of custom logic or instantiate a block of preverified
Intellectual Property (IP), make assignments to that block, verify
functionality and performance, lock the block to maintain this placement
and performance, and then export the block to be imported into another
design. In this way, blocks can be designed, tested, and optimized
individually and can maintain their performance when integrated into a
larger design.
In addition, by saving intermediate synthesis results into a VQM File and
replacing the entity with the VQM File in the project when you import the
assignments, you ensure that the node names synthesized in the new project
correspond to the node names in the imported assignments.
The following steps describe the basic flow for saving intermediate synthesis
results as a VQM File, back-annotating assignments, and exporting and
importing QSFs for designs that contain LogicLock regions:
1. Create LogicLock regions.
2. Compile the design.
3. Use the Back-Annotate Assignments (Advanced type) dialog box
(Assignments menu) to lock the logic placement in the LogicLock
region(s).
4. Export the LogicLock region assignments to a QSF by using the Export
Assignments dialog box (Assignments menu).
5. Instantiate the module in the VQM File into a top-level design and
import the LogicLock region assignments by using the Import
Assignments dialog box (Assignments menu). Click LogicLock Import
File Assignments to specify the name of the QSF that contains the
LogicLock region assignments, the entity name in the QSF that you are
importing, and the entity name in the design to which you are applying
the assignments.
!
Save Intermediate Synthesis Results Only for Bottom-Up LogicLock
Design Flows
You should save intermediate synthesis results to a VQM File only if you are using
a bottom-up LogicLock design flow, and should not save them if you are using a top-
down incremental compilation flow with LogicLock regions. The top-down
incremental compilation flow saves synthesis and fitting results in the project
database.