Specifications

CHAPTER 6: BLOCK-BASED DESIGN
SAVING INTERMEDIATE SYNTHESIS RESULTS FOR BOTTOM-UP LOGICLOCK FLOWS
120 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
After the initial or setup compilation, Altera recommends that you set the
Size to Fixed in order to yield better f
MAX
results. If device utilization is low,
increasing the size of the LogicLock region may allow the Fitter additional
flexibility in placement and may produce better final results.
When you perform an incremental compilation, the fitting and synthesis
results and settings for design partitions are saved in the project database.
For more information about assigning design partitions, refer to “Assigning
Design Partitions” on page 62 in Chapter 3, “Constraint Entry.”
For more
information about incremental compilation, refer to “Top-Down
Incremental Compilation Flow” on page 30 in Chapter 1, “Design Flow.” and
“Performing a Full Incremental Compilation” on page 92 in Chapter 5,
“Place & Route.”
Saving Intermediate Synthesis
Results for Bottom-Up LogicLock
Flows
You can save synthesis results for individual entities in conjunction with the
bottom-up LogicLock design flows by creating a Verilog Quartus Mapping
File (.vqm) for an entity in a design, with a corresponding QSF that contains
the LogicLock constraint information for the entity.
f
For Information About Refer To
Using Quartus II incremental
compilation with LogicLock regions
“LogicLock Design Methodology,” in the
Quartus II Handbook, vol. 2, on the Altera
web site
“Quartus II Incremental Compilation,” in the
Quartus II Handbook, vol. 1, on the Altera
web site
“Overview: Using Incremental Compilation”
in Quartus II Help